Technical Field
The present subject matter generally relates to semiconductor integrated circuits, and more particularly, to an architecture for redundant memory cells in memory devices, including memory devices utilizing three-dimensional circuit techniques.
Background Art
Some integrated circuits (ICs), including dedicated memory devices, include blocks of memory cells. While traditional memory devices organize the cells in a two dimensional array, some devices may include a three dimensional array of cells. In some three dimensional flash memories, a NAND string may be built vertically, stacking the individual field-effect transistors (FETs) of the string on top of each other, so that the string extends out from the substrate. Such architectures may provide for very high bit densities in a flash memory device. A side-effect of these large three dimensional structures is that since the number of defects may be proportional to the total area of the various layers and a three dimensional memory may have many layers, the total area that may contain a defect is much larger than a similarly sized two dimensional array, leading to a lower yield in manufacturing.
Redundant memory cells have been used to improve yields. In some architectures, additional memory cells have been provided to implement error correction codes, such as hamming codes, to correct single bit errors, or even multi-bit errors, in a word or other sized parallel access of the memory array. Other architectures have included redundant rows or columns of the memory array that could be mapped to replace a complete row or column that is found to be defective.